Field of the Invention
The present invention relates to an imaging apparatus.
Description of the Related Art
A solid imaging apparatus has been known that includes a comparator unit comparing a predetermined level of an analog pixel signal obtained from a pixel with a reference signal that gradually changes for converting the predetermined level into digital data (e.g., see Japanese Patent Application Laid-Open No. 2008-136043). A count unit performs a counting process in parallel with a comparison process in the comparator unit, and holds a count value at the time when the comparison process is ended, thereby acquiring digital data at the predetermined level. A reference signal generating unit changes the slope of the reference signal according to a signal from a communication and timing control unit.
An analog-digital converter has been known that includes a latch circuit for a higher order bit and a latch circuit for a lower order bit, and quantizes the higher order bit and the lower order bit separately from each other (e.g., see Japanese Patent Application Laid-Open No. 2002-232291). First, a pixel signal is supplied to one input terminal of a comparator provided for each column. A staircase wave having a large voltage step is supplied to the other input terminal as a reference voltage. A count value corresponding to the number of steps when the output of the comparator is inverted is held in a latch circuit as a higher order bit. Meanwhile, the reference voltage at this time is held in a capacitor. Subsequently, a reference voltage having a small voltage step is supplied via the capacitor, and a count value at the time when the comparator is inverted again is held in the latch circuit for the lower order bit.
According to Japanese Patent Application Laid-Open No. 2008-136043, the slope of the reference signal changes according to the signal of the communication and timing control unit. Accordingly, there is a possibility that the count value of the count unit on each column has a different value when the slope of the reference signal changes. In this case, it is difficult to design timing between the slope of the reference signal and the count value of the counter unit. When the slope of the reference signal is changed, the clock signal is also required to be changed. Accordingly, the circuit size of the counter unit becomes large.